Inverter circuits for driving loads such as motors correspond to DC/AC converters which convert DC voltages to AC voltages so as to supply the converted AC voltages to the motors, namely the loads. Inverter circuits for driving inductive motors are arranged by, for instance, insulated gate bipolar transistors (IGBTs) corresponding to switching elements, and free wheel diodes (FWDs). In one inverter circuit, an IGBT is employed as a switching element, and an FWD bypasses/circulates a current which flows through a motor while the IGBT is turned OFF in order that the current flowing through the motor is not changed by switching operations of the IGBT. More concretely speaking, a DC power supply is connected to the motor, if the IGBT which has applied the voltage to the motor is turned OFF, then the current which has flown through the motor passes through the FWD to flow as a reverse DC current due to energy stored in an inductance “L” of the motor. Thus, the motor is brought into a status equivalent to such a condition that the reverse DC voltage is applied to the motor. As a consequence, the current of the motor is not rapidly interrupted by switching the IGBT, so that the AC voltage can be essentially applied from the DC power supply by the switching operation.
IGBTs corresponding to the structural elements of the above-described inverter circuits are mainly classified into a so-called “punch through (PT)” type IGBT, a non-punch through (NPT) type IGBT, and a field stop (FS) type IGBT. The field stop (FS) type IGBT is disclosed in JP-A-2004-103982, and corresponds to an intermediate type IGBT with respect to a PT type IGBT and an NPT type IGBT. A PT type IGBT has such a structure that a P conductivity type (P+) substrate having a thick thickness is employed as a collector layer, and an N conductivity type (N+) buffer layer has been inserted between the collector layer and an N conductivity type (N−) drift layer. An NPT type IGBT has such a structure that a P conductivity type (P+) collector layer has been formed on a rear plane of an N conductivity type (N−) substrate (body layer) having a thin thickness and functioning as a drift layer. Also, an FS type IGBT has such a structure that a buffer layer has been inserted between a drift layer and a collector layer of an NPT type IGBT, and the N conductivity type (N−) substrate (body layer) corresponding to the drift layer has be made thinner. The above-described buffer layer is called as a field stop (FS) layer, and N conductivity type carrier concentration has been designed as low concentration.
As previously described, IGBTs and FWDs have been combined with each other in inverter circuits. Very recently, in order to make the above-described inverter circuits compact, such semiconductor devices have been considered which have been manufactured by parallel-forming IGBT cells and diode cells in a single semiconductor substrate. These semiconductor devices have been disclosed in, for example, JP-A-2005-57235 and JP-A-6-196705. JP-A-2005-57235 has disclosed a semiconductor device manufactured by that an NPT type IGBT is formed in combination with a diode. JP-A-6-196705 has disclosed another semiconductor device manufacture by that both an NPT type IGBT and a PT type IGBT are formed in combination with a diode.
FIG. 14 is a sectional view for schematically indicating a conventional semiconductor device 90, namely a semiconductor device manufactured by that a PT type IGBT has been formed in combination with a diode, which is similar to the semiconductor device disclosed in JP-A-6-196705.
In the semiconductor device 90 shown in FIG. 14, an IGBT and a diode cell have been parallel-formed in a single semiconductor substrate 1. In this semiconductor device 90 of FIG. 14, a region 90i surrounded by a dot and dash line corresponds to the IGBT cell, whereas a region 90d surrounded by a two-dot and dash line corresponds to the diode cell. In this drawing, equivalent circuit symbols have been superimposed with respect to the respective regions to be illustrated. The IGBT 90i is expressed as a structure in which an MOS transistor 90m and a bipolar transistor 90b have been connected to each other in a manner as shown in this drawing. A current flowing through the MOS transistor 90m constitutes a base current of the bipolar transistor 90b. 
In the semiconductor device 90 of FIG. 14, an N conductivity type (N−) first semiconductor layer (body layer) 1a formed from the major plane of the semiconductor substrate 1 up to the vicinity of the rear plane thereof is a drift layer of carrier of the IGBT 90i and the diode 90d. A P conductivity type (P+) second semiconductor layer 2 formed in a surface layer portion of the semiconductor substrate 1 on the side of the rear plane-thereof is a collector layer of the IGBT 90i (emitter layer of bipolar transistor 90b). Also, in an N conductivity type (N+) third semiconductor layer 3 formed by covering the second semiconductor layer 2, a region 3a functions as a cathode electrode connection layer of the diode 90d, and another region 3b located over the second semiconductor layer 2 functions as a buffer layer 3b of the IGBT 90i. The region 3a is connected to an electrode of the rear plane and is adjacent to the second semiconductor layer 2.
While the IGBT formed in the semiconductor device 90 of FIG. 14 has the PT type IGBT structure having the buffer layer 3b, since the N body layer 1a corresponding to the drift layer of the carrier can be made thinner, there is a merit that an ON voltage which constitutes the basic characteristic of the IGBT can be lowered.
On the other hand, the Inventors of the present patent application could reveal the below-mentioned problem as a result of analyzing of characteristics as to the semiconductor device 90 of FIG. 14. That is, in the semiconductor device 90 having such a structure that the IGBT 90i having the FS layer (namely, buffer layer) 3b and the diode 90d have been parallel-formed in one semiconductor substrate 1, a snap back occurs in a current-to-voltage (Ic-Vce) characteristic which constitutes a basic characteristic of an IGBT.
FIG. 15 is a diagram for schematically representing the above-described problem as to the occurrence of the snap back in the current-to-voltage (Ic-Vce) characteristic.
In a normal IGBT where a snap back does not occur, as indicated by a solid line “XVA” in this drawing, when a voltage VCE is increased from 0 V, a current Ic rises at a threshold voltage VCE(th) of approximately 0.4 to 0.8 V. To the contrary, in an IGBT where a snap back occurs, as shown by an arrow solid line “XVB” of this drawing, even when the voltage VCE is increased from 0 V, the current IC does not rise from the voltage VCE of several V up to approximately 10 V When the voltage VCE reaches an operating point “XVC (VCE1, IC1)”, the voltage VCE jumps up to another operating point “XVD” in a discontinuous manner, and the voltage VCE drops, and then, the current IC suddenly rises. This discontinuous characteristic corresponds to a snap back phenomenon. A drop voltage VSB shown in FIG. 15 is referred to as a “snap back voltage.”
IGBTs where snap backs occur can be hardly controlled. For example, if a snap back happens to occur in IGBTs which are connected parallel to each other, then a distribution of currents becomes unbalanced. As a result, parallel operations of the IGBTs may be troubled. In such a parallel connection system of these IGBTs, in order that essential trouble does not occur in the parallel operations, the snap back voltage VSB is required to be lower than at least the threshold voltage VCE(th).
In other words, in a semiconductor device manufactured by that an IGBT cell having a low ON-voltage and a diode cell have been parallel-formed in a single semiconductor substrate, it is required to suppress an occurrence of a snap back.